library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity RAM is
generic (DATA	: integer := 32;
             ADDR	: integer := 2);
port( 	clock		: in   std_logic;
		reset		: in   std_logic;
		vliw_en		: in   std_logic;
		write_en		: in   std_logic;
		write_en_vliw	: in   std_logic;
		addr_in		: in   std_logic_vector (ADDR-1 downto 0);
		addr_in_vliw	: in   std_logic_vector (ADDR-1 downto 0);
		data_in		: in   std_logic_vector (DATA-1 downto 0);
		data_in_vliw	: in   std_logic_vector (DATA-1 downto 0);
		data_out		: out std_logic_vector (DATA-1 downto 0);
		data_out_vliw	: out std_logic_vector (DATA-1 downto 0)
        );
end entity RAM;

architecture Behavioral of RAM is
type ram_type is array(0 to (2 ** ADDR)-1) of std_logic_vector(DATA-1 downto 0);
signal ram : ram_type;
begin

process (clock, reset,vliw_en)
begin

	if (reset = '1') then
		for i in 0 to (2 ** ADDR)-1 loop
			ram(i) <= (others => '0');
		end loop;
	elsif rising_edge(clock) then
		if write_en = '1' then
			ram(to_integer(unsigned(addr_in))) <= data_in;
		end if;
		if vliw_en = '1' and write_en_vliw = '1' then
			ram(to_integer(unsigned(addr_in_vliw))) <= data_in_vliw;
		end if;
	end if;
    
end process;

data_out		<= ram(to_integer(unsigned(addr_in)));
data_out_vliw	<= ram(to_integer(unsigned(addr_in_vliw))) when vliw_en = '1'
			      else (others => '0');

end Behavioral;
